High Performance IIR Filter Design Based on Fast Multiplier
DOI:
https://doi.org/10.24237/djes.2025.18111Keywords:
IIR filter, FPGA, HDL, BCD multiplier, Mux-MultiplierAbstract
This paper presents an optimal new method to design infinite impulse response (IIR) digital filters through implementing and comparing various multiplier architectures in order to opt the best approach among them. The reason behind focussing on the multiplier unit belongs to its essential role in the performance of the IIR filters. Direct form II is the realization form opted to characterize the suggested IIR filter which is coded, using Quartus II software and subdued to gate level simulation on field programmable gate array (FPGA) kit board. The proposed IIR filter, whose architecture includes the binary coded decimal (BCD) involved in it, has gained the best outcomes. The BCD multiplier is compared to other multipliers such as: array multiplier, parallel multiplier with two-splitting of Booth and parallel circuits, Vedic multiplier and Mux-Multiplier which are implemented with the Cyclone IV GX FPGA kit platform. It was observed that BCD-multiplier has recorded the smallest logic elements (188) along with the fastest operation speed (282.8 MHz) and the lowest delay time (7.89 ŋSec) compared to other approaches. The IIR filter circuit designed with the BCD multiplier is programmed and implemented on the Cyclone IV GX FPGA kit platform. Depending on the obtained results, the IIR filter based BCD-multiplier has promising features that make it more attractive than IIR systems based on other multipliers. Moreover, these features make the IIR filter widely exploited in diverse electronic systems and devices such as: images and biomedical signal processing applications, communications and radar systems.
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[20] K. Susmitha, V.K., S. K. Saha and R. Kar, Optimal Design of IIR Band pass and Band stop Filters using GSA-BBO Technique and Their FPGA Implementation, in In Proceedings of the 2020 International Conference on Communication and Signal Processing (ICCSP). 2020: Chennai, India. p. 1106-1110, doi: 10.1109/ICCSP48568.2020.9182242.
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[22] Datta, D., Dutta, H.S., High performance IIR filter implementation on FPGA. . Journal of Electrical Systems and Inf Technol, 2021. 8(2): p. 1-9, doi: 10.1186/s43067-020-00025-4.
[23] Abdulnabi, Y.S.M.a.S.H., High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing," in Proceedings of the 2023 5th International Congress on Human-Computer Interaction, Optimization and Robotic Applications (HORA). 2023: Istanbul, Turkiye. p. 1-6, doi: 10.1109/HORA58378.2023.10156676.
[24] Nayak S, N.M., Matri S, Sharma KP., Synthesis and Analysis of Digital IIR Filters for Denoising ECG Signal on FPGA, in in Proceedings of the Evolving Networking Technologies: Developments and Future Directions. . 2023, Willy. p. 189-210, doi: 10.1002/9781119836667.ch12.
[25] S. A. Loan, A. M. Murshid and F. Bashir, "A novel VLSI architecture of a defuzzifier unit for a fuzzy inference processor," in Proceedings of the 2013 International Conference on Advanced Electronic Systems (ICAES), Pilani, India, 2013, p. 138-141, doi: 10.1109/ICAES.2013.6659378.
[26] F. Bashir, F. Zahoor, A. S. Alzahrani and A. R. Khan, "A Single Schottky Barrier MOSFET-Based Leaky Integrate and Fire Neuron for Neuromorphic Computing," in Proceedings of the IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 11, Nov. 2023, p. 4018-4022, doi: 10.1109/TCSII.2023.3286810.
[27] Khanday, M.A., Khanday, F.A. & Bashir, F. Single SiGe Transistor Based Energy-Efficient Leaky Integrate-and-Fire Neuron for Neuromorphic Computing. Neural Process Lett 55, 2023, p. 6997–7007, doi: 10.1007/s11063-023-11245-w.
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[31] Alkurwy Salah, A.H., Isam, Implementation of High Performance Convolution Based on Novel Mux-Multiplier. International Review on Modelling and Simulations (IREMOS), 2024. 17: p. 1-5, doi: 10.15866/iremos.v17i1.23073.
[32] Alkurwy, S., Design and Implementation of Parallel Multiplier Using Two Split Circuits, Przegląd Elektrotechniczny 2021: p. 1-4, doi: 10.15199/48.2021.07.04.
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[34] Salah Alkurwy, S.A.-A., Noor Al Darraji, FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier. International Review on Modelling and Simulations (IREMOS.), April 2019. 12(2): p. 66-71, doi: 10.15866/iremos.v12i2.16322.
[35] P. Bharade, Y.J.a.R.M., Design and implementation of IIR lattice filter using floating point arithmetic in FPGA, in In Proceedings of the 2016 Conference on Advances in Signal Processing (CASP). 2016: Pune, India. p. 321-326, doi: 10.1109/CASP.2016.7746188.
[36] P. S. Howal, K.P.U.a.M.C.P., HDL implementation of digital filters using floating point vedic multiplier, in Proceedings of the 2017 IEEE International Conference on Circuits and Systems (ICCS) 2017, IEEE: Thiruvananthapuram, India. p. 274-279, doi: 10.1109/ICCS1.2017.8326004.
[37] V. Pathak, S.J.N., A. M. Joshi and S. S. Sahu, High Speed Implementation of Notch/Anti-notch IIR Filter on FPGA, in In Proceedings of the 2018 15th IEEE India Council International Conference (INDICON). 2018: Coimbatore, India p. 1-6, doi: 10.1109/INDICON45594.2018.8986985.
[1] Nguyen, D.M. and S. Kim, The fog on: Generalized teleportation by means of discrete-time quantum walks on N-lines and N-cycles. Modern Physics Letters B, 2019. 33(23): p. 1950270, doi: 10.1142/s0217984919502701.
[2] S., C., Design and Realization of IIR Digital Band Stop Filter Using Modified Analog to Digital Mapping Technique. International Journal of Science, Engineering and Technology Research (IJSETR), 2013. 2(3): p. 742-748, https://www.slideshare.net/slideshow/3-design-and-realization-of-iir-digital-band-stop-filter-using-modified-analog-to-digital-mapping-technique/27375581.
[3] YOUSFIALAOU, M., ECG denoising by EMD and EEMD improved with an adaptive RLS filter. . International Journal of Advanced Trends in Computer Science and Engineering, 2020. 9(3): p. 3241-3248, doi:10.30534/ijatcse/2020/118932020.
[4] Kansal, M., FPGA Implementation of IIR Filter after Checking Feasibility using Matlab & Modelsim. International Journal of Electronics & Communication Technology, 2011. 2(4): p. 146-151, https://www.iject.org/vol2issue4/manish.pdf.
[5] A. Paul, T.Z.K., P. Podder, M. M. Hasan and T. Ahmed, Reconfigurable architecture design of FIR and IIR in FPGA, in In Proceedings of the 2nd International Conference on Signal Processing and Integrated Networks (SPIN), Noida. 2015: India, . p. 958-963, doi.org/10.1109/SPIN.2015.7095408,
[6] DSchlichthärle, Digital Filters. Basics and Design, ed. -.n. Ed-s. 2010, Frankfurt, Main, Germany: Springer, doi:10.100.7/978-3-662-04170-3.
[7] A. Madanayake, L.B., y C. Comis, FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters, in In Proceedings of the 2004 IEEE International Symposium on Circuits and Systems, 2004, IEEE: Vancouver, BC, Canada. p. 613–616, doi: 10.1109/ISCAS.2004.1328821.
[8] C. Zhao y Z. Zhang, Digital filter design and performance analysis of dynamic temperature signal denoise based on FPGA, in In Proceedings of the 2016 10th International Conference on Sensing Technology (ICST). 2016, IEEE: Nanjing, China. p. 1–7, doi: 10.1109/ICSensT.2016.7796285.
[9] R. Dhannawat1, e.a., A New Faster, Better Pixels Weighted Don’t Care Filter for Image Denoising and Deblurring. Int. J. of Advanced Trends in Computer Science and Engineering, 2020. 9(2): p. 2302-3209, doi: 10.30534/ijatcse/2020/212922020.
[10] R. Landry, V.C.a.E.R., High speed IIR filter for XILINX FPGA, in In Proceedings of the 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268). 1998: Notre Dame, IN, USA p. 46-49, doi: 10.1109/MWSCAS.1998.759432.
[11] K. Limnuson, H.L., H. J. Chiel and P. Mohseni, FPGA implementation of an IIR temporal filtering technique for real-time stimulus artifact rejection, in In Proceedings of the 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS). 2011, IEEE: San Diego, CA, USA, p. 49-52, doi: 10.1109/BioCAS.2011.6107724.
[12] S. M. Rabiul Islam, R.S., S. Saha and A. F. M. Nokib Uddin, Design of a programmable digital IIR filter based on FPGA, in In Proceedings of the 2012 International Conference on Informatics, Electronics & Vision (ICIEV). 2012: Dhaka, Bangladesh. p. 716-721, doi: 10.1109/ICIEV.2012.6317409.
[13] E. C. Vivas González, D.M.R.P.a.E.J.G., Implementation and simulation of IIR digital filters in FPGA using MatLab system generator, in In Proceedings of the 2014 IEEE 5th Colombian Workshop on Circuits and Systems (CWCAS), Bogota, Colombia. 2014, IEEE. p. 1-5, doi: 10.1109/CWCAS.2014.6994612.
[14] D. C. Toledo-Pérez, M.A.M.-P., J. Rodríguez-Reséndiz, S. Tovar Arriaga and M. Á. Marquez-Gutiérrez, IIR digital filter design implemented on FPGA for myoelectric signals, in In Proceedings of the 2017 XIII International Engineering Congress (CONIIN). 2017: Santiago de Queretaro, Mexico. p. 1-7, doi: 10.1109/CONIIN.2017.7968184.
[15] Seshadri R, R.S., FPGA implementation of fast digital FIR and IIR filters. Concurrency and Computation: Practice and Experience. Willy . 2019, p 1-11, doi: 10.1002/cpe.5246.
[16] Ashok, P.P.a.S., IIR Digital Filter Design Using Xilinx System Generator for FPGA Implementation, in In Proceedings of the 2018 International Conference on Communication and Signal Processing (ICCSP). 2018, IEEE: Chennai, India. p. 0054-0057, doi: 10.1109/ICCSP.2018.8524520.
[17] A. K. Yadav, B. C. Nagar and G. Pradhan, "FPGA Implementation of IIR Notch and Anti-Notch Filters With an Application to Localization of Protein Hot-Spots," in IEEE Transactions on NanoBioscience, vol. 22, no. 4, pp. 863-871, Oct. 2023, doi: 10.1109/TNB.2023.3238733..
[18] Serhienko, A.S.a.A., VHDL Generation of Optimized IIR Filters, in In Proceedings of the 2019 IEEE 2nd Ukraine Conference on Electrical and Computer Engineering (UKRCON). 2019, IEEE: Lviv, Ukraine. p. 1171-1174, doi: 10.1109/UKRCON.2019.8880009.
[19] Z. Qiang, S.J., W. Weilian, Y. Ruping and C. Cheng, Design of fourth-order IIR digital filter based on FPGA, in In Proceedings of the 2019 14th IEEE International Conference on Electronic Measurement & Instruments (ICEMI). 2019, IEEE: Changsha, China. p. 161-166, doi: 10.1109/ICEMI46757.2019.9101857.
[20] K. Susmitha, V.K., S. K. Saha and R. Kar, Optimal Design of IIR Band pass and Band stop Filters using GSA-BBO Technique and Their FPGA Implementation, in In Proceedings of the 2020 International Conference on Communication and Signal Processing (ICCSP). 2020: Chennai, India. p. 1106-1110, doi: 10.1109/ICCSP48568.2020.9182242.
[21] Serhienko, A.S.a.A., Complexity Reduced IIR Filter Design for FPGA, in In Proceedings of the 2020 IEEE 2nd International Conference on System Analysis & Intelligent Computing (SAIC). 2020, IEEE: Kyiv, Ukraine p. 1-4, doi: 10.1109/SAIC51296.2020.9239119.
[22] Datta, D., Dutta, H.S., High performance IIR filter implementation on FPGA. . Journal of Electrical Systems and Inf Technol, 2021. 8(2): p. 1-9, doi: 10.1186/s43067-020-00025-4.
[23] Abdulnabi, Y.S.M.a.S.H., High Performance FIR and IIR Filters Based on FPGA for 16 Hz Signal Processing," in Proceedings of the 2023 5th International Congress on Human-Computer Interaction, Optimization and Robotic Applications (HORA). 2023: Istanbul, Turkiye. p. 1-6, doi: 10.1109/HORA58378.2023.10156676.
[24] Nayak S, N.M., Matri S, Sharma KP., Synthesis and Analysis of Digital IIR Filters for Denoising ECG Signal on FPGA, in in Proceedings of the Evolving Networking Technologies: Developments and Future Directions. . 2023, Willy. p. 189-210, doi: 10.1002/9781119836667.ch12.
[25] S. A. Loan, A. M. Murshid and F. Bashir, "A novel VLSI architecture of a defuzzifier unit for a fuzzy inference processor," in Proceedings of the 2013 International Conference on Advanced Electronic Systems (ICAES), Pilani, India, 2013, p. 138-141, doi: 10.1109/ICAES.2013.6659378.
[26] F. Bashir, F. Zahoor, A. S. Alzahrani and A. R. Khan, "A Single Schottky Barrier MOSFET-Based Leaky Integrate and Fire Neuron for Neuromorphic Computing," in Proceedings of the IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 11, Nov. 2023, p. 4018-4022, doi: 10.1109/TCSII.2023.3286810.
[27] Khanday, M.A., Khanday, F.A. & Bashir, F. Single SiGe Transistor Based Energy-Efficient Leaky Integrate-and-Fire Neuron for Neuromorphic Computing. Neural Process Lett 55, 2023, p. 6997–7007, doi: 10.1007/s11063-023-11245-w.
[28] Beguenane, N.C.a.R., FPGA-Based 8x8 Bits Signed Multipliers Using LUTs, in In Proceedings of the 2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE). 2023, IEEE: Regina, SK, Canada. p. 366-370, doi: 10.1109/CCECE58730.2023.10288715.
[29] Rajeev, A.A.W.a.S.P., Implementation of an Array Multiplier Using an Addition Algorithm with Signed Digit Representation, In Proceedings of the 2023 7th International Conference On Computing, Communication, Control and Automation (ICCUBEA). 2023: Pune, India. p. 1-4, doi: 10.1109/ICCUBEA58933.2023.10392006.
[30] V. Lakshmi, J.R.a.V.P., A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. in Proceedings of the IEEE Transactions on Circuits and Systems I: Regular Papers, March 2022. 69( 3): p. 1148-1158, doi: 10.1109/TCSI.2021.3129827.
[31] Alkurwy Salah, A.H., Isam, Implementation of High Performance Convolution Based on Novel Mux-Multiplier. International Review on Modelling and Simulations (IREMOS), 2024. 17: p. 1-5, doi: 10.15866/iremos.v17i1.23073.
[32] Alkurwy, S., Design and Implementation of Parallel Multiplier Using Two Split Circuits, Przegląd Elektrotechniczny 2021: p. 1-4, doi: 10.15199/48.2021.07.04.
[33] Alkurwy, S., A novel approach of multiplier design based on BCD decoder. Indonesian J Elec Eng & Comp Sci, April 2019 :. 14: p. 38 – 44, doi: 10.11591/ijeecs.v14.i1.pp38-43.
[34] Salah Alkurwy, S.A.-A., Noor Al Darraji, FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier. International Review on Modelling and Simulations (IREMOS.), April 2019. 12(2): p. 66-71, doi: 10.15866/iremos.v12i2.16322.
[35] P. Bharade, Y.J.a.R.M., Design and implementation of IIR lattice filter using floating point arithmetic in FPGA, in In Proceedings of the 2016 Conference on Advances in Signal Processing (CASP). 2016: Pune, India. p. 321-326, doi: 10.1109/CASP.2016.7746188.
[36] P. S. Howal, K.P.U.a.M.C.P., HDL implementation of digital filters using floating point vedic multiplier, in Proceedings of the 2017 IEEE International Conference on Circuits and Systems (ICCS) 2017, IEEE: Thiruvananthapuram, India. p. 274-279, doi: 10.1109/ICCS1.2017.8326004.
[37] V. Pathak, S.J.N., A. M. Joshi and S. S. Sahu, High Speed Implementation of Notch/Anti-notch IIR Filter on FPGA, in In Proceedings of the 2018 15th IEEE India Council International Conference (INDICON). 2018: Coimbatore, India p. 1-6, doi: 10.1109/INDICON45594.2018.8986985.
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